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!M%R)MFo_u55 V ]5U E5 (assert error): cause=0x%x, epc=0x%x
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x%u: 0x%x
sp%u: 0x%x
Exception error: cause=0x%x, mepc=0x%x
Caller regs
%u: 0x%x
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== Aeonsemi Inc ==
19:15:28 Nov 18 2025 Build %s at %s %s.
wdtornmi 20230714 ERROR: not match:cu-an start:%u, dpc start:%u
total spent time is large:%u us
O (null) ABad fmt_str
Invalid element size dioxXu eEfFgG %s
%s
NONE BUF UART BUF, UART INFO DEBUG ERROR: Parameter %s (maximum: %d)
ERROR: Parameter %s is beyond %d chars
ERROR: Parameter %s is beyond %u chars
Command "%s" is not found!
as2101# %c [2K
ERROR: Command queue is full! ERROR: The character "%x" is invalid!
I I I I I I I I I I I I J *J J >J fJ J J K K &K G zD6N PN XN N bN vN |N N N N N N N N &N N O O O IPC read size too large: %d
Version "%s"
ireboot
csum : %u
image_sum : %u
enable : %u
valid : %u
oui_start : %u
ss_start : %u
temp_mon_start : %u
Invalid log level %d
Cannot change dest. of log level %d.
Log levels above %d are compiled out.
P P Q R R PX PX TS TS PX nS S S S S FT PX T PX T T PX pV V W W BX PX PX PX PX PX PX @U RU U U 0Q 8Q BQ \Q vQ Q R custom_var_len_big: %u
custom_cmd_err: %u %u
PY \Y jY rY |Y Y Y Y Y 4Z >Z FZ LZ RZ fZ lZ rZ xZ pit interrup, save usr cfg
\ \ @] @] @] @] @] @] @] @] @] \ \ ] @] @] @] *] M >L N ? $tI10G Ability : %u
ERR:sample_cin_phase=%d
sample_cin_phase_1=%d
sample_cin_phase_2=%d
phase_wrap_cnt=%d
kint=%d
bw_synce=%d
chk_point : %d %d
chk_point_aux : %d %d
strobe : %d %d
duration : %d
dft_bin : %d
done : %d
min : max : avg : var : xcorr : psd : dft_rp : dft_ip :
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ף:MVL3310 AQC107 AQC107_STC AQC107_AUKUA AQC113C AQC413C BCM8489x BCM8488x AEON BCM8485x BCM8484x Intel UNKNOWN s t s t 0t @t Pt `t pt t t t t error: read back interval is different: %u %u
error: glb fcnt time out!
FL(kL @ F @ NC:NNPRBS rx_prbs_st is SYNC
PRBS rx_prbs_st is out of SYNC
PRBS count %llu
PRBS error count %u
PRBS count %llu after clear
PRBS error count %u after clear
PRBS check pass
PRBS check fail
FRM_CNT : %u
CRC_CNT : %u
Enable second serdes clock
$tI $tI 2 $tI @ C @B @ B B A kA A A @ A B @C @ D @ @ sds-an arb_state: %u
@ tx_nrm_lpi_offset is not 63: %d
rx_nrm_lpi_offset is not 63: %d
pmang_restart_ldpc_dec
---------------------------
GPMA | GDSP | A | B | C | D
0x%-2X | 0x%-2X | %u | %u | %u | %u
MSE : [%d, %d, %d, %d]
A ffe_1st : %d %d %d %d
FFE : [%d, %d, %d, %d]
FFE_AVG : %d
FFE_CHA : %d
AGC_FINAL : %d
CHAN_LEN : [%d, %d, %d, %d]
CHAN_LEN_AVG : %d
[%u] 1000bt_eee_entered
[%u] 1000bt_eee_exited
[%u] 1000bt_eee_failed
[%u] 100tx_eee_entered
[%u] 100tx_eee_exited
[%u] 100tx_eee_failed
cur_ts: %d
sr_depth : %d
sr_ts_rd: %d
2 sr_ts: %d B B A (# (#* *0 08 8t@ t@\D \D N NW Wc cHq Hq܂ ܂| | @ clk_err : 1
(knM L@(knN nEWzLInfoField # rxinfo_PMA_state: %d
rxinfo_loc_rcvr_status: %d
rxinfo_en_slave_tx: %d
rxinfo_trans_to_Coeff_Exch: %d
rxinfo_cur_pbo: %d
rxinfo_cur_valid: %d
rxinfo_req_pbo: %d
rxinfo_req_valid: %d
rxinfo_nxt_pbo: %d
rxinfo_nxt_valid: %d
rxinfo_transition_cnt: %d
rxinfo_snr_margin: %d
rxinfo_trans_to_fine_adjust: %d
rxinfo_trans_to_pcs_test: %d
rxinfo_coeff_exchange: %d
< f %s: Incorrect filter type %d specified
fdae_mmem_write @ EB=Wݴ 8q5` :±qӱ ? total_num_cw_decoded : %llu
total_num_cw_failed : %d
avg_ber_approx : %.6f
avg_ber_rough : %.6f
avg_iter : %.3f
avg_cycles : %.3f
max_iter : %.3f
min_ber_est : %.6f
max_ber_est : %.6f
total_cw_synd_wt_layer_end : %d
min_cw_synd_wt_layer_end : %d
max_cw_synd_wt_layer_end : %d
avg_layer_end_synd_wt : %.3f
last_failed_cw_idx0 : %d
last_failed_cw_idx1 : %d
last_failed_cw_idx2 : %d
last_failed_cw_avg_ber : %.6f
last_failed_cw_synd_wt_first_layer : %d
last_failed_cw_synd_wt_layer_end : %d
avg_zero_llr : %.3f
iter_histogram : %d %d
*P .P *P 4P 4P 4P .P *P *P .P 0P 2P 4P 4P 0P 4P 4P 4P 4P 4P 4P 4P 4P 4P 4P 4P 4P 4P 4P 4P 2P dP fP fP fP fP dP fP fP dP bP `P ^P fP bP link_partner : 0x%2x
A pA>> >>\? +? ?
ERROR append_timer_active: already active: %p
ERROR attach_timer: no space left
H^ ] ] ^ $^ L^ h^ ] ] adc_avg : %d %d %d %d
adc_rms rxfd_dout_rms * test_mode : %d
tone : %d
^ ^ ^ ._ 6_
` 4` z` a ` ` ` ` ` ` sys_mh_train SYS_MH_TRAIN_IDLE SYS_MH_TRAIN_FC_AFE_INIT SYS_MH_TRAIN_FC_AFE_START SYS_MH_TRAIN_FC_AFE_WAIT SYS_MH_TRAIN_TDD_POST_FC_AFE SYS_MH_TRAIN_FORK_FDAE_BLW SYS_MH_TRAIN_POST_CANCEL SYS_MH_TRAIN_TEST_MODE SYS_MH_TRAIN_DONE SYS_MH_TRAIN_ERROR a a a a a a a a a b b b b a Fb `b b b b b a WARN pga_gain_range_fail : %x
pga_atten : %d %d %d %d
pga_fb_res : %d %d %d %d
ifft_sig_error : %d
rx_train_rms ffe_rms_pre ffe_rms_post pk_adj : %x
mf_fc_afe_align_dp_snr scr_lock_dp_snr ffe_align_dp_snr cdr_ffe : chan_dly : %d %d %d %d
mf_train_dp_snr c_d_swap : %d
debug: 10G eee will be disable
rx_signal_detect b c Xc `c xc d e f b tf f f g @g Tg vg g g g th h sys_mf_train SYS_MF_TRAIN_IDLE SYS_MF_TRAIN_RX_SIGNAL_DETECT SYS_MF_TRAIN_CHAN_EST SYS_MF_TRAIN_FC_AFE_SNAPSHOT SYS_MF_TRAIN_ADJ_PGA SYS_MF_TRAIN_FCAFE_RESCL SYS_MF_TRAIN_FCAFE_FDAE_RESETTLE SYS_MF_TRAIN_RX_PATH_INIT SYS_MF_TRAIN_CDRNG SYS_MF_TRAIN_CANCELLER_RESCALE SYS_MF_TRAIN_FC_AFE_REALIGN SYS_MF_TRAIN_SCR_RESET SYS_MF_TRAIN_SCR_LOCK SYS_MF_TRAIN_MDI_FAULT SYS_MF_TRAIN_REFTRAIN_ALIGN SYS_MF_TRAIN_REFTRAIN_EN SYS_MF_TRAIN_FFE_ALIGN SYS_MF_TRAIN_RESETTLE_CDR_FFE SYS_MF_TRAIN_COPY_CDR_FFE SYS_MF_TRAIN_PROCEED SYS_MF_TRAIN_DONE SYS_MF_TRAIN_ERROR j j j j j j j j j j j xk k k Pk xj `k |k k k k k k k xj sh_train_ffe_only_dp_snr sh_train_dp_snr test_mode : %d
tone : %d
speed : 0x%x
l l %s
[%u] ERROR: %s:%s
ERROR: FSM %s does not have a state named "%s"!
pma_state : %d
lz rz z z z z z { &{ t{ { { z { ms_cfg : %u
speed : %u
mdi : %u
trd : %d
pre_cfr_cnt : %d
pre_cfr_fail_cnt : %d
pmang_loc_rcvr_status : 0
| | } } ~ 2~ d~ ~~ ~ ~ & : | Z ng_phyctrl PHYCTRL_DISABLE_TRANSMITTER PHYCTRL_INIT_MAXWAIT_TIMER PHYCTRL_SILENT PHYCTRL_MH_TRAIN PHYCTRL_SH_TRAIN PHYCTRL_MF_TRAIN PHYCTRL_SF_TRAIN PHYCTRL_PBO_EXCH PHYCTRL_COEFF_EXCH PHYCTRL_FINE_ADJUST PHYCTRL_PCS_TEST PHYCTRL_PCS_DATA PHYCTRL_DONE PHYCTRL_INIT_FR PHYCTRL_ERROR echo_next_res : %d %d %d %d
echo_next_mse : %d %d %d %d
chkpt_thresh : %d
| Ă Ђ curr_gear : %d
check_iter : %d
echo_next_dp_snr echo_clip next_clip res_scale_error : %d
echo_blk0_max : %d %d %d %d
next_blk0_max : %d %d %d , nblk_echo : %d
nblk_next : %d
L> D `DN V ̆ F : L Љ sys_echo_next SYS_ECHO_NEXT_IDLE SYS_ECHO_NEXT_SETUP SYS_ECHO_NEXT_GEAR_SHIFTING SYS_ECHO_NEXT_CMEM_RESCALE SYS_ECHO_NEXT_MSE_CHECK SYS_ECHO_NEXT_LMD_CHECK SYS_ECHO_NEXT_CMEM_CHECK SYS_ECHO_NEXT_DONE SYS_ECHO_NEXT_ERROR intg_avg : %d
ڊ ( 6 D R ` d r ފ sh_cdr_gain_adapt_b_c_d_dp_snr cdr_dp_snr : %.2f %.2f %.2f %.2f
pch_lch_a : %d %d
Z b
F n Ѝ . V V sys_sh_cdr SH_CDR_IDLE SH_CDR_START SH_CDR_CHECK_LOCK SH_CDR_GAIN_ADAPT_CH_A SH_CDR_FFE_ADAPT_CH_A SH_CDR_RESCALE_CH_A SH_CDR_INIT_BEST_CH_A SH_CDR_GAIN_ADAPT_CH_B_C_D SH_CDR_FFE_ADAPT_CH_B_C_D SH_CDR_RESCALE_CH_B_C_D SH_CDR_INIT_BEST_CH_B_C_D SH_CDR_REDUCE_BW SH_CDR_FINAL_ADAPT SH_CDR_PD_ERR_MSE SH_CDR_DONE SH_CDR_ERROR * & F > ` n r mf_cdr_init_dp_snr mf_cdr_rescale_dp_snr ` n x ܓ sys_mf_cdr MF_CDR_IDLE MF_CDR_START MF_CDR_INIT_CDRNG MF_CDR_FDAE_SETTLE MF_CDR_FDAE_GEARSHIFT MF_CDR_INIT_FFE MF_CDR_FFE_RESCALE_COARSE MF_CDR_RESCALE MF_CDR_SWAP_MAIN_FFE MF_CDR_FINAL_SETTLE MF_CDR_ERR_MSE MF_CDR_DONE MF_CDR_ERROR tdd_anon_fsm starting timer 0x%p for duration %d usec. Current ticks %llu
tdd_anon_fsm: measurement completed. Timer 0x%p state %d, elapsed %d, remain %d. Current ticks %llu
tdd_anon_fsm: measurement timed out. Current ticks %llu
ANONYMOUS FSM: %s:
Current state: %s
ANON FSM INFO: %s
TDD_FSM_IDLE TDD_FSM_WAIT g g CMEM_RD_IDLE CMEM_RD_AWAIT_SNAPSHOT CMEM_RD_DATA_XFER g g g ޘ , X \ n x ʘ pbo_dp_snr rx_pbo_rms loc_req_nxt : %d %d
lp_req_nxt : %d %d
pbo_err : %x
lp_eee_ability : %d
fr_abt : %d
loc_thp_byp : %d
rem_thp_byp : %d
rx_pam2_mv_rms : %.2f %.2f %.2f %.2f
F D ښ $ L v
sys_pbo_exch SYS_PBO_EXCH_IDLE SYS_PBO_EXCH_WAIT SYS_PBO_EXCH_SEND_REQ_S2M SYS_PBO_EXCH_UPDATE_NEXT SYS_PBO_EXCH_TRANS_SETUP SYS_PBO_EXCH_TRANS_START SYS_PBO_EXCH_TRANS_WAIT SYS_PBO_EXCH_POST SYS_PBO_EXCH_DONE SYS_PBO_EXCH_ERROR CMEM Wr FSM - Writing tone %u
CMEM_WR_IDLE CMEM_WR_DATA_XFER \ ު έ sys_chan_est SYS_CHAN_EST_IDLE SYS_CHAN_EST_INIT SYS_CHAN_EST_DFT_RUN SYS_CHAN_EST_DFT_UPDATE SYS_CHAN_EST_COMPUTE_LEN SYS_CHAN_EST_DONE SYS_CHAN_EST_ERROR ERROR: SH_SOFT_FFA_RUN_REFINE
* 0 4 ` grid_iter : %d
refine_trials : %d
ppm_offset : %.3f
.AЯ ԯ x sys_sh_soft_ffa SH_SOFT_FFA_IDLE SH_SOFT_FFA_INIT SH_SOFT_FFA_GRID_UPDATE SH_SOFT_FFA_RUN_GRID SH_SOFT_FFA_REFINE SH_SOFT_FFA_RUN_REFINE SH_SOFT_FFA_DONE SH_SOFT_FFA_ERROR N T X f t R phyctrl_st : %d
pcsng hw pcs_st : %d
pcs_test_clip : %d
block_lock : %d
high_ber : %d
pcs_test_fail_dp_snr cmem_echo cmem_next cmem_fext training_time_period: %d ms
pcs_test_dp_snr total fail cw num:%d
` d P X r \ sys_pcs_test link_fail_alert_thd %u, %u
SYS_PCS_TEST_IDLE SYS_PCS_TEST_SETUP SYS_PCS_TEST_FLUSH SYS_PCS_TEST_MONITOR SYS_PCS_TEST_CAPTURE SYS_PCS_TEST_LINK_UP SYS_PCS_TEST_DONE SYS_PCS_TEST_ERROR link_st : %d
hw_block_lock : %d
hw_high_ber : %d
sw_lfer_cnt : %d
pcs_data_error_dp_snr slc_rms v r z r v r r retrain : 0x%x
lfer_cw_step : %d
lfer_timestep : %d
pcs_data_dp_snr dp_snr : %.2f %.2f %.2f %.2f
ch : %d
efilt_coeffs_init :
efilt_coeffs_new :
fc_afe_dir : %d %d %d %d
fc_afe_arr : %0x
dual : %d
xch : %d
blk : %d
pk_echo : %d %d
pk_next : %d %d
pk_fext : %d %d
fext_rscl_ch_xch_tap_val : %d %d %d %d
*WARN loc_fr_detect : %d
loc_fr_req : %d
pre_fr_dp_snr rx_pwr_err : %x
pcs_hi_lfer : %d
pcs_data_lfer_dp_snr : %.2f %.2f %.2f %.2f
@ Z < p " sys_pcs_data SYS_PCS_DATA_IDLE SYS_PCS_DATA_SETUP SYS_PCS_DATA_WAIT SYS_PCS_DATA_RX_PWR_LOSS SYS_PCS_DATA_LINK_STATUS SYS_PCS_DATA_REPORT SYS_PCS_DATA_INIT_SETTLE_DONE SYS_PCS_DATA_FCAFE_MON SYS_PCS_DATA_LDPC_MON SYS_PCS_DATA_SW_CDR SYS_PCS_DATA_ISO_RECALC SYS_PCS_DATA_CMEM_RESCL SYS_PCS_DATA_FEXT_RESCL SYS_PCS_DATA_CLIP SYS_PCS_DATA_DONE SYS_PCS_DATA_RX_LPI SYS_PCS_DATA_RX_LPI_WAKEUP SYS_PCS_DATA_WAKE_FAIL SYS_PCS_DATA_ERROR tx_blw_pole_freq : %d %d %d %d
b N l L Z ^ l z X sys_tx_blw TX_BLW_IDLE TX_BLW_SETUP TX_BLW_INIT_SETTLE TX_BLW_ALPHA_SETTLE TX_BLW_ALPHA_FREEZE TX_BLW_DONE TX_BLW_ERROR *TIMER EXPIRE 6 J ` h v ms_cfg : %d
duplex : %d
speed : %d
mdi_mode : %d
mdi_sel : %d
mdi_status : %d
ng_mdi_sync : %d
ng_mdi_cfg : %d
rx_addon_st : %d
rx_cw : 0x%04x%04x%04x
tx_addon_st : %d
tx_cw : 0x%04x%04x%04x
( n T h z n z n f ^ P x . : AUTONEG_ENABLE TRANSMIT_DISABLE ABILITY_DETECT ACKNOWLEDGE_DETECT COMPLETE_ACKNOWLEDGE NEXT_PAGE_WAIT LINK_STATUS_CHECK PARALLEL_DETECTION_FAULT FLP_LINK_GOOD_CHECK FLP_LINK_GOOD SYS_CU_AN_FW_IDLE SYS_CU_AN_FW_RESTART SYS_CU_AN_FW_AUTO_NEG_ENABLE SYS_CU_AN_FW_FORCE_MODE_ENABLE SYS_CU_AN_FW_TX_DISABLE_WAIT SYS_CU_AN_FW_TX_DISABLE SYS_CU_AN_FW_PROCESSING SYS_CU_AN_FW_LINK_GOOD_CHECK SYS_CU_AN_FW_FLP_LINK_GOOD SYS_CU_AN_FW_PAR_DET_FAULT SYS_CU_AN_FW_LINK_STS_CHK SYS_CU_AN_FW_LINK_STS_CHK_WAIT 8 & J ^ & p & & 4 & J ^ & p & & 0 & J ^ & p & & gphy eee ability is disable
sr_limit : %d
datamode_mse : %d %d %d %d
freqofst_ppm : %.3f %.3f
FINAL_FFE_AVG : %d
[%u]*GPHY: mse degradated
degradation_mse_d : %d %d %d %d
degradation_mse : %d %d %d %d
degradation_power_d : %d %d %d %d
degradation_power : %d %d %d %d
FreqOfst_A_ppm: %.3f
2 $ * j GPHY_TX_DISABLE GPHY_ENABLE GPHY_ADC GPHY_MTRAIN GPHY_STRAIN GPHY_RETRAIN GPHY_100M GPHY_100M_AGC GPHY_SCAN_FOR_CARRIER GPHY_DONE GPHY_M_RETRY GPHY_S_REINIT GPHY_S_WAIT N T b d t b ~ mhtrain_mse : %d %d %d %d
agc_gain_final : %d
mftrain_scan_cnt : %d
mftrain_scan_num : %d
ffe : %d %d %d %d
mtrain->cfg.agc_gain_mes : %d
bestoffset_mse : %d %d %d %d
finetrain_mse : %d %d %d %d
finetune_redo_cnt = %d
traindone_mse : %d %d %d %d
P 8 * gphy_m GPHY_MT_IDLE GPHY_MT_INIT GPHY_MT_MFTRAIN GPHY_MT_MFTRAIN_AGC_EST GPHY_MT_MFTRAIN_AGC GPHY_MT_MFTRAIN_DAC GPHY_MT_MFTRAIN_AGC_DONE GPHY_MT_MFTRAIN_DFE GPHY_MT_MFTRAIN_FINETUNE GPHY_MT_MFTRAIN_FINETUNE_CHECK GPHY_MT_TRAINDONE_SCR_CHECK GPHY_MT_MFTRAIN_REDO GPHY_MT_DONE 4 J T ` n strain->cfg.agc_gain_mes : %d
freq_ofst_ovrd : %d
shtrain_mse : %d %d %d %d
freqofst_ppm_sh : %.3f %.3f
sftrain_mse : %d %d %d %d
, x 6 gphy_s GPHY_ST_IDLE GPHY_ST_INIT GPHY_ST_SHTRAIN_AGC_CFG GPHY_ST_SHTRAIN_AGC_MEAS GPHY_ST_SHTRAIN_SHIFTCLK_BCD GPHY_ST_SHWAIT_DAC GPHY_ST_SHWAIT_DONE GPHY_ST_SHWAIT_WAIT_DONE GPHY_ST_FINETUNE GPHY_ST_DONE gphy_adc GPHY_ADC_IDLE GPHY_ADC_INIT GPHY_ADC_SHIFT GPHY_ADC_DONE rx_crc_err_cnt : %d
ffe_pk_idx : %d %d %d %d
eslc_fifo_dly: %d %d %d %d
rx_fifo_fill : %d %d %d %d
( 6 D H V f j D , < \ l | Received coefficients = InfoField TX successful fr_relock_dp_snr fr_fdae_opt_dp_snr fc_afe_realign : 0x%1x
rx_gain_final : %d %d %d %d
echo_next_rms : %u %u %u %u
ce ifft_dout_rms : %d %d %d %d
thp_ffe : thp_coeffs : pre_exch_dp_snr ce_snr_margin : %.1f
rx_coeff_exch_rms coeff_exch_dp_snr lp_thp_coeffs : 0 ~ H l . N " L 4 ^ , ` > sys_coeff_exch SYS_COEFF_EXCH_IDLE SYS_COEFF_EXCH_WAIT SYS_COEFF_EXCH_FR_FDAE_ADAPT SYS_COEFF_EXCH_FR_EQ_CFR_ADAPT SYS_COEFF_EXCH_FR_CFR_READY SYS_COEFF_EXCH_FR_EQ_IEEE_ADAPT SYS_COEFF_EXCH_FR_IEEE_READY SYS_COEFF_EXCH_WAIT_HOLDOFF SYS_COEFF_EXCH_RESTART_CDRNG SYS_COEFF_EXCH_CDRNG_LOW_BW SYS_COEFF_EXCH_SCR_RESET SYS_COEFF_EXCH_SCR_LOCK SYS_COEFF_EXCH_REFTRAIN_ALIGN SYS_COEFF_EXCH_REFTRAIN_EN SYS_COEFF_EXCH_WAIT_TIMING_OK SYS_COEFF_EXCH_TIMING_OK SYS_COEFF_EXCH_FDAE_START SYS_COEFF_EXCH_RESETTLE_CANCEL SYS_COEFF_EXCH_SLAVE_REACQUIRE SYS_COEFF_EXCH_SLAVE_GAIN_REFINE SYS_COEFF_EXCH_SLAVE_FFE_REFINE SYS_COEFF_EXCH_SLAVE_ACK SYS_COEFF_EXCH_RXGAIN_CHECK SYS_COEFF_EXCH_IFFT_RESCALE SYS_COEFF_EXCH_EXTEND_ECHO_NEXT SYS_COEFF_EXCH_FDAE_GEARSHIFT SYS_COEFF_EXCH_FINAL_JOINT SYS_COEFF_EXCH_FFE_RESCALE_FINE SYS_COEFF_EXCH_EXTEND_JOINT SYS_COEFF_EXCH_WAIT_READY SYS_COEFF_EXCH_PROCESS SYS_COEFF_EXCH_TRANS_SETUP SYS_COEFF_EXCH_TRANS_START SYS_COEFF_EXCH_TRANS_WAIT SYS_COEFF_EXCH_POST SYS_COEFF_EXCH_DONE SYS_COEFF_EXCH_ERROR $ J 2 ^ n z 2 aux_ffe_swap_dp_snr fext_sum : %d %d %d %d
pre_fine_trans_dp_snr fa_snr_margin : %.1f
fine_adjust_dp_snr rx_mv_rms : %.2f %.2f %.2f %.2f
near_xtalk_db : %.2f l X ~ X F ~ T " P P P P P P P : : P f sys_fine_adjust >SYS_FINE_ADJUST_IDLE SYS_FINE_ADJUST_WAIT SYS_FINE_ADJUST_START_FEXT SYS_FINE_ADJUST_AUX_FFE SYS_FINE_ADJUST_RE_FFE SYS_FINE_ADJUST_FINISH_FEXT SYS_FINE_ADJUST_IEEE_FR_SETUP SYS_FINE_ADJUST_SETTLE SYS_FINE_ADJUST_ISO_UPDATE SYS_FINE_ADJUST_EXTEND_FINAL SYS_FINE_ADJUST_TRANS_SETUP SYS_FINE_ADJUST_TRANS_START SYS_FINE_ADJUST_TRANS_WAIT SYS_FINE_ADJUST_POST SYS_FINE_ADJUST_DONE SYS_FINE_ADJUST_ERROR check_iters : %d
clip_fext_%d : %d %d %d
fext_error_dp_snr "
8
F
P
n
B
%2d pre_fext_dp_snr fext_gear_pre_dp_snr fext_rescale_pre_dp_snr fext_cmem_rescale : 0x%x
fext_iter_dp_snr fext_mse_check_dp_snr fext_cmem_dp_snr fext_clip fext_en : %d
ntap_fext : %d
fext_cancel_dp_snr ?p
|
j 0 sys_fext SYS_FEXT_IDLE SYS_FEXT_DISABLE SYS_FEXT_SETUP SYS_FEXT_CFR_IDLE SYS_FEXT_CFR_SETUP SYS_FEXT_GEAR_SHIFTING SYS_FEXT_CMEM_RESCALE SYS_FEXT_MSE_CHECK SYS_FEXT_LMD_CHECK SYS_FEXT_CMEM_CHECK SYS_FEXT_DONE SYS_FEXT_ERROR gphy_dac GPHY_DAC_IDLE GPHY_DAC_INIT GPHY_DAC_SHIFT GPHY_DAC_DONE 2 h datarate : %u
pcs_mode : %u
xfi_mode : %u
ppm_ofst : %d
cdr_ppm : %.3f
rx_loss_of_signal 6 n " J SYS_SDS_TX_DISABLE SYS_SDS_TX_DISABLE_WAIT SYS_SDS_ENABLE SYS_SDS_CDR_REL SYS_SDS_VGA SYS_SDS_EDGE SYS_SDS_CTLE SYS_SDS_DFE SYS_SDS_LPBK SYS_SDS_TEST_MODE SYS_SDS_DATA sds sds2nd 1G 2.5G 5G 10G SYS_SDS_AN_WAIT_START SYS_SDS_AN_ENABLE SYS_SDS_AN_ERROR SYS_SDS_AN_RESTART SYS_SDS_AN_ABT_DETECT SYS_SDS_AN_ACK_DETECT SYS_SDS_AN_ACK_COMPLETE SYS_SDS_AN_WAIT_LINK_OK SYS_SDS_AN_IDLE_DETECT SYS_SDS_AN_LINK_OK SYS_SDS_AN_DIS_LINK_OK link_up : %u
duplex : %u
speed : %u
eee_cap : %u
clk_stop : %u
%s to AN_RESTART
AN link down
" p# " " " " `" # @# `# # $ # # $ ($ # v$ $ $ sds-an pkt_err_hang err_type %u hang_cnt %u err_old %u err_new %u
%llu : %u
cfg_ra_en : %u
D @ state : %u
link_up : %u
duplex : %u
eee_cap : %u
init_sds_an
pcs unlocked, restart sds
*to_sds_restart , , , Z- f- - - - . , . . V- X. h. crc_chg_high %s_pkt_rate : %u
crc_chg_low from_eth from_sds mac_rx_idx : %u
mac_rx_%u : %llx, %llx, %llx
fifo_hang rx-fifo : %u
tx-fifo : %u
sds_tx_dis : %u
crc_err : %u
mac-rx : %u
ldpc_err : %u
re_an_now : 1
Packet_Error_Mon frm_cnt : %u, crc_err : %u, %u
ldpc_cw : %llu, ldpc_err : %u, %u
reset_fifo auto_eee_update auto_eee_init eth_link_up : %u
ra_rising_edge : %u
eth_spd : %u
delay : %u
done Enable CU_IF Loopback
Release CU _F Loopback
exit_data_mode_hw_reset auto_eee_disable
enter_data_mode_hw_release wait_send_pkt : %u
enter sds_link_ok send_pkt *exit_data_mode_hw_reset *enter_data_mode_hw_release ; $; ~; ; f< ; < <= "> B> ^> B> = = > > > > > > > ? > B > C Disable Enable Clock Only PCS PMA SGMII USXGMII SYS_DPC_INIT SYS_DPC_WAIT_EHT_DATA_MODE SYS_DPC_SDS_RESTART SYS_DPC_SDS_GE_PATH SYS_DPC_SDS_WAIT_DATA_MODE SYS_DPC_SDS_WAIT_LINK SYS_DPC_SDS_RESTART_AN SYS_DPC_MAC_IF_READY SYS_DPC_SDS_INIT_CLOCK SYS_DPC_DATA_PATH_READY SYS_DPC_RATE_ADAPT_WAIT SYS_DPC_ETH_PKT_GEN_READY SYS_DPC_SDS_EN_MAC_AN SYS_DPC_PHY_IF_WAIT SYS_DPC_PHY_IF_READY SYS_DPC_DONE E E E E &F E 2F ability : 0x%x
fail_cnt : %u
fail_cnt : %d
retry_limit : %u
disable_speed : 0x%x
ZF lF F F 6G bG G smartspd SMART_SPD_FSM_IDLE SMART_SPD_FSM_INIT_WAIT SMART_SPD_FSM_INIT SMART_SPD_FSM_LINK_CHECK SMART_SPD_FSM_LINK_GOOD SMART_SPD_FSM_LINK_FAIL SMART_SPD_FSM_DONE H H H H H rx_blw_pole_freq : %d %d %d %d
rx_blw_gain : %.3f %.3f %.3f %.3f
:H H hI I I J sys_rx_blw RX_BLW_IDLE RX_BLW_START RX_BLW_PAUSE RX_BLW_RESETTLE RX_BLW_FREEZE RX_BLW_DONE RX_BLW_ERROR K L 0L :L K TL 6L PL 0M :M >M >M L *M L L bM M M M M M nbt_abi : 0x%0x
Current_msg_cnt of tx_msg out of bounds
Current_msg_cnt of rx_msg out of bounds
link_partner : O O P 0P O P DQ R R OUI_AN_IDLE OUI_AN_ENABLE_WAIT OUI_AN_GE_XNP OUI_AN_ENABLE OUI_AN_TRIGGER_SOFTNP OUI_AN_PAGE_RCV_WAIT OUI_AN_ACK_WAIT OUI_AN_ABILITY_RESO OUI_AN_DONE
@ -C 6:?clk_meas MPNuNMMONMLMOMuMLCMCOC:NNLCMC:OCMM4LMNM(kLKCLK_MEAS_IDLE CLK_MEAS_START CLK_MEAS_CAP CLK_MEAS_DONE V V lV xV V V V V V Exceeding safe temperature, downshift to 5G
V W 6W ^W W XW W X X X SYS_TEMP_MON_IDLE SYS_TEMP_MON_BIN_SEARCH_INIT SYS_TEMP_MON_BIN_SEARCH_SETTLE SYS_TEMP_MON_BIN_SEARCH SYS_TEMP_MON_LIN_SEARCH SYS_TEMP_MON_VDIO_MEAS_SETTLE SYS_TEMP_MON_VDIO_MEAS SYS_TEMP_MON_TEMP_CALC SYS_TEMP_MON_WAIT SYS_TEMP_MON_DONE Y Y Y Y Z Z Y :Z @Z [ x enable : %d
ability : %d
ldpc : %d
pbo : %d
auto_mdi_dis : %d
man_mdi_val : %d
& 6 D R ` p ̑ ڑ validity : %d
temperature : %d
start : %d
mode : %d
alarm_thres : %d
self_protect_en : %d
RA_ENA = %u
TX_IPG = %u
< x ޓ V h < pcs_sel : %d
spd_sel : %d
op_mode : %d
from_eth_pkt_rate : %u packets/s
from_sds_pkt_rate : %u packets/s
from_eth_pkt_rate_flag : %u
from_sds_pkt_rate_flag : %u
vco_ppm = %d
sds_ppm = %d
ҕ ܕ ` ̗ 2 @ ~ ֘ $ chan_len(m) : %d, %d, %d, %d
freq_offset : %d
snr_margin : %d, %d, %d, %d
chan_skew : %d, %d, %d, %d
dfe_coeffs_ch%d : %d,
echo_response: chan_len : %d, %d, %d, %d
imp_type : %s, %s, %s, %s
res_conf : 0x%x
t ę ܙ 0 SDS RX LOS VTH: %u
DFE adaptation done
SDS_%u Equalization Pre-Setting:
VGA[%u, %u] CTLE[%u, %u] DFE[%u, %u, %u]
restart_sds_an
This Chip does not support Second Serdes
f H T T , 0 ֝ | Ĝ ޜ * v > " H z ҟ , , $ num_grps : %u
cols_grp : %u
vert_res : %u
num_samp : %u
0x%02x Second Serdes configuration
SDS PMA PRBS Check : %u
SDS PMA TXFIR setting
Pre-Cursor : %d
Main-Cursor : %d
Post-Cursor : %d
SDS Adatation Result:
VGA : %u, %u
CTLE : %u, %u
DFE : %u, %u, %u
Auto-EEE configuration:
enable : %u
idle_th : %u
rx_eyevth_cal : %u
pre-corr : %d
main-corr : %d
post-corr : %d
ġ x x ڡ ( x x x auto_link_ena : %u
auto_link_cfg : %u
@@
0 Data Mode:
%4u EEE Mode:
set ifft rms tgt:%u-%u-%u
mdi_trd : %d %d
chan_map : %d %d %d %d
hy_efilt_peak : %.3f %.3f %.3f %.3f
= adc_fifo : %d %d %d %d
rt_dly_x2 : %d %d %d %d
cal_fifo : %d %d %d %d
dly_adj : %d %d %d %d
tx_efilt : hyec : C 4<)d?q? F <̽> %s_echo_scale : %d %d %d %d
%s_echo_blk : , %s_next_scale : %d %d %d, %d %d %d, %d %d %d, %d %d %d
%s_next_blk_%d : %s_dac_gain : %d %d %d %d
%s_ifft_sig : %d %d %d %d
%s_ifft_exp : %d %d %d %d
> I DFEXT FIR statistics A @ DR@ ? 6;? 8B 9 @ r?q[@T-@ Aq[?b> A?@ j*
*j ERROR: echo/NEXT ISO FW FFT timed out: %d
ERROR: FEXT ISO FW FFT timed out: %d
CMEM statistics lp_fft_echo_next : %d
lpfft_fext_ref_err : %d
lpfft_fext_err_err : %d
lmd_echo_next_%d : %u %u %u
lmd_fext_%d : %s_ch%d : 0x%x 0x%1x 0x%1x 0x%1x %d, %d, %d ]ZH @ Cf
AFEXT datapath scales mr_scram_ok : %x
frame_cs : %x
frame_lock : %x
ref_train_en_swap : %x
lock_dim : %d%d%d
cnt_skew_b : %d
cnt_skew_c : %d
cnt_skew_d : %d
polarity : %x
scr_ntrial : %d
align_ntrial : %d
ref_ntrial : %d
ffe_ntrial : %d
lock : %x
FFE peaks eslc_dly : %s : %.2f %.2f %.2f %.2f
%s : %d %d %d %d
ffe : dfe : ? ?(> ch%u_gain_norm : %u, %u %u %f
clip_det : 0x %02x echo_cmem : next_cmem : %d %d %d %d fext_cmem : %d, %d, %d
ffe_filt_dpath : 0x%2x
ffe_ae : 0x%2x%2x%2x%2x dfe_ae : 0x%2x%2x gain_norm_main : 0x%2x
gain_norm_cdrng : 0x%2x
hyec_cancel : 0x%2x
hyec_cancel_dc : 0x%1x
hyec_ae : 0x%2x%2x%2x
tx_efilt : 0x%2x, 0x%2x, 0x%2x, 0x%2x
hy_efilt : 0x%2x, 0x%2x, 0x%2x, 0x%2x
tx_dac_mis : 0x %2x hy_dac_mis : 0x System busy: %d %d %d %d
%s : "%s" isn't recognized!
Available commands:
comm ver readmem writemem writereg led fastmdc oui fsm_ngphy fsm_gphy fsm_cu_an fsm_dpc fsm_ss fsm_oui_an fsm_temp_mon fsm_mdi fsm_auto_link fsm_cable_diag
FW version: %s
Build commit: %08x
19:15:40 AEON_NBT.BIN build time : %s %s
Read %08x: %04x %08x
%s is not 10 chars addr don't start with 0xea Size of log: %u
Info of Link Partner : M/S cfg : %u
MDI cfg : %u
EEE Status :
100M : %u, 1G : %u, 2.5G : %u, 5G : %u, 10G : %u
Fast Retrain Status :
SDS-AN Link Status : %u
VCO PPM : %d
SDS PPM : %d
tx_full_scale_%u : irq query status: 0x%x
ERR_BLOCKS : %u
BER_CNT : %u
HIGH_BER : %u
BLOCK_LOCK : %u
WAKE_ERR_CNT: %u
tx_cs : %u, rx_cs : %u
pma : %u, dsp : %u
Unknown debug command: %2x
$ B D v en rst ms dplx top_spd fr_thp eee_adv trd pdet get_cfg an_cnt clr_an_cnt get_status en_10m testmode cdrbw_set cdrbw_get eee_status cfr_cnt clr_cfr_cnt ldpc_wakeup wake_timer pam16_set pam16_get lfer_get ifft_rms_tgt fa_dp_snr_thresh normal_retrain_abi tm5_gain get_mode set_mode set_break clr_break list_break get_state set_state list_state set_verb list_child start stop swdt nbt_set aeon_set nbt_get aeon_get cfr_set set_mode get set_thresh pro_en get_cfg set set get ra_set set_pkt fifo_rs ra_fifo_rs pkt_rate pkt_dir set get set eye_scan auto_eee_set eye_get sds_rst_an sds2nd_enable sds2nd_cfg sds2nd_cfg_get testmode auto_eee_get vga slc ctle dfe eee_en pcs_prbs_set pcs_sqwav_set pcs_err_chk pcs_tst_freq pma_prbs_set pma_prbs_chk pol txfir_set txfir_get get_eq dfe_fine_tune los_vth_set los_vth_get eyevth_set eyevth_get eye_corr_get chan_len ppm_offset snr_margin chan_skew dfe bkgd_en echo set_full_diag get_full_diag enable link-type get en mode usr_bw slave_clk_output_ctrl master_kffkint slave_bwkint print cdr_dbg -DAE350 -DAEON_IMAGE -DBOOT_MDIO -DWITH_UART -DWITH_IPC -DLOG_LVL=1 -DFW -DSYS_FW_OPT -DREVB1 2025-11-18 191540 1.9.1 M ? G A F M G A F 0@P`p @BDF @BDF
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